`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:04:21 01/26/2013
// Design Name:   ppstoremanager
// Module Name:   E:/ParaCPU/shaoxia-project/hdl/src/tb_modules/tb_ppstoremanager.v
// Project Name:  ise_ParaCPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ppstoremanager
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`include "s:/define.v"
module tb_ppstoremanager;

	// Inputs
	reg clk;
	reg rst_n;
wire [32*64-1:0] pps_wr_data;
wire  [30*64-1:0] pps_wr_addr;

reg [31:0]unpack_pps_wr_data[63:0];
reg [29:0]unpack_pps_wr_addr[63:0];
reg [5: 0] pps_max_indx; 
 genvar unpk_idx;genvar pk_idx;
`PACK_ARRAY(32,64,64,unpack_pps_wr_data,pps_wr_data,p1,p2)
`PACK_ARRAY(30,64,64,unpack_pps_wr_addr,pps_wr_addr,p3,p4)

reg [64-1:0] pps_wr_data_en;
wire [64-1:0]pps_wr_data_consumed;
wire [4-1:0] ext_ram_wr_en;
wire  [32*4-1:0] ext_ram_wr_data;
wire  [28*4-1:0] ext_ram_wr_addr;

wire [31:0] unpack_ext_ram_wr_data[3:0];
wire [27:0] unpack_ext_ram_wr_addr[3:0];
`UNPACK_ARRAY(32,4,4,unpack_ext_ram_wr_data,ext_ram_wr_data,p5,p6)
`UNPACK_ARRAY(28,4,4,unpack_ext_ram_wr_addr,ext_ram_wr_addr,p7,p8)

reg [64-1:0] pps_busy;
reg sp_wr_en;
reg [31:0] sp_wr_data;
reg [31:2] sp_wr_addr;
wire sp_wr_data_consumed;
	// Instantiate the Unit Under Test (UUT)
	ppstoremanager
	#(.PP_NUM_LOG2(6),.EXT_RAM_BANKS_NUM_LOG2(2))
	uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.pps_wr_data(pps_wr_data),
		.pps_wr_addr(pps_wr_addr),
		.pps_wr_data_en(pps_wr_data_en),
		.pps_wr_data_consumed(pps_wr_data_consumed),
		.ext_ram_wr_en(ext_ram_wr_en),
		.ext_ram_wr_data(ext_ram_wr_data),
		.ext_ram_wr_addr(ext_ram_wr_addr),
		.pps_max_indx(pps_max_indx),
		
		.pps_busy(pps_busy),
		.sp_wr_en(sp_wr_en),
		.sp_wr_data(sp_wr_data),
		.sp_wr_addr(sp_wr_addr),
		.sp_wr_data_consumed(sp_wr_data_consumed)
	);
integer i;
	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;
		pps_wr_data_en<=0;
		pps_max_indx=31;
		sp_wr_en<=0;
		sp_wr_data<=0;
		sp_wr_addr<=0;
		pps_busy<=16'hFF;
		for(i=0;i<64;i=i+1)
            begin
                unpack_pps_wr_data[i]<=i;
					 unpack_pps_wr_addr[i]<=i;
            end
		// Wait 100 ns for global reset to finish
		#100 rst_n=1;
		
		pps_wr_data_en<=64'h6007;
        
		// Add stimulus here
		#1000 pps_busy<=0;
		sp_wr_en<=1;
		sp_wr_data<=32'h112233;
		sp_wr_addr<=32'h445566;
	end
always #2 clk=~clk;
endmodule

